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december 2000 1 ? 2000 actel corporation v4.0.1 act ? 2 family fpgas features up to 8000 gate array gates (20,000 pld equivalent gates) replaces up to 200 ttl packages replaces up to eighty 20-pin pal ? packages design library with over 500 macro functions single-module sequential functions wide-input combinatorial functions up to 1232 programmable logic modules up to 998 flip-flops datapath performance at 105 mhz 16-bit accumulator performance to 39 mhz two in-circuit diagnostic probe pins support speed analysis to 50 mhz two high-speed, low-skew clock networks i/o drive to 10 ma nonvolatile, user programmable logic fully tested prior to shipment 1.0-micron cmos technology product family profile device a1225a a1240a a1280a capacity gate array equivalent gates pld equivalent gates ttl equivalent packages 20-pin pal equivalent packages 2,500 6,250 63 25 4,000 10,000 100 40 8,000 20,000 200 80 logic modules s-modules c-modules 451 231 220 684 348 336 1,232 624 608 flip-flops (maximum) 382 568 998 routing resources horizontal tracks/channel vertical tracks/channel plice antifuse elements 36 15 250,000 36 15 400,000 36 15 750,000 user i/os (maximum) 83 104 140 packages 1 100 cpga 100 pqfp 100 vqfp 84 plcc 132 cpga 144 pqfp 176 tqfp 84 plcc 176 cpga 160 pqfp 176 tqfp 84 plcc 172 cqfp performance 2 16-bit prescaled counters 16-bit loadable counters 16-bit accumulators 105 mhz 70 mhz 39 mhz 100 mhz 69 mhz 38 mhz 85 mhz 67 mhz 36 mhz notes: 1. see the ?product plan? on page 3 for package availability. 2. performance is based on ??2? speed devices at commercial worst-case operating conditions using prep benchmarks, suite #1, ver sion 1.2, dated 3-28-93, any analysis is not endorsed by prep. .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 2v4.0 description the act ? 2 family represents actel ? s second generation of field programmable gate arrays (fpgas). the act 2 family presents a two-module architecture, consisting of c-modules and s-modules. these modules are optimized for both combinatorial and sequential designs. based on actel ? s patented channeled array architecture, the act 2 family provides significant enhancements to gate density and performance while maintaining downward compatibility with the act 1 design environment and upward compatibility with the act 3 design environment. the devices are implemented in silicon gate, 1.0-m, two-level metal cmos, and employ actel ? s plice ? antifuse technology. this revolutionary architecture offers gate array design flexibility, high performance, and fast time-to-production with user programming. the act 2 family is supported by the designer and designer advantage systems, which offers automatic pin assignment, validation of electrical and design rules, automatic placement and routing, timing analysis, user programming, and diagnostic probe capabilities. the systems are supported on the following platforms: 386/486 ? pc, sun ? , and hp ? workstations. the systems provide cae interfaces to the following design environments: cadence, viewlogic ? , mentor graphics ? , and orcad ? . ordering information application (temperature range) c = commercial (0 to +70c) i = industrial (?40 to +85c) m = military (?55 to +125c) b = mil-std-883 package type pl = plastic j-leaded chip carrier pq = plastic quad flat pack cq = ceramic quad flat pack pg = ceramic pin grid array tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack speed grade blank = standard speed ?1 = approximately 15% faster than standard ?2 = approximately 25% faster than standard part number a1225 = 2500 gates a1240 = 4000 gates a1280 = 8000 gates die revision a = 1.0-m cmos process package lead count a1280 ? pg 176 c 1 a .com .com .com .com .com 4 .com u datasheet
v4.0 3 act ? 2 family fpgas product plan device resources . speed grade* application std ? 1 ? 2cimb a1225a device 100-pin ceramic pin grid array (pg) 100-pin plastic quad flat pack (pq) 100-pin very thin (1.0 mm) quad flat pack (vq) 84-pin plastic leaded chip carrier (pl) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a1240a device 132-pin ceramic pin grid array (pg) 176-pin thin (1.4 mm) quad flat pack (tq) 144-pin plastic quad flat pack (pq) 84-pin plastic leaded chip carrier (pl) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a1280a device 176-pin ceramic pin grid array (pg) 176-pin thin (1.4 mm) quad flat pack (tq) 160-pin plastic quad flat pack (pq) 172-pin ceramic quad flat pack (cq) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? contact your actel sales representatives for product availability. applications: c = commercial availability: ? = available *speed grade: ? 1 = approx. 15% faster than standard i =industrial p =planned ? 2 = approx. 25% faster than standard m= military ? = not planned b=mil-std-883 user i/os device series logic modules gates cpga pqfp plcc cqfp tqfp vqfp 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin a1225a 451 2500 ?? 83 ?? 83 72 ?? 83 a1240a 684 4000 ? 104 ?? 104 ? 72 ? 104 ? a1280a 1232 8000 140 ?? 125 ?? 72 140 140 ? .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 4v4.0 operating conditions absolute maximum ratings 1 free air temperature range electrical specifications recommended operating conditions symbol parameter limits units v cc dc supply voltage ? 0.5 to +7.0 v v i input voltage ? 0.5 to v cc +0.5 v v o output voltage ? 0.5 to v cc +0.5 v i io i/o source/sink current 2 ?0 ma t stg storage temperature ? 65 to +150 c notes: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5 v or less than gnd ? 0.5 v, the internal protection diode will be forward biased and can draw excessive current. parameter commercia l industria l military units temperature range 1 0 to +70 ? 40 to +85 ? 55 to +125 c power supply tolerance ? ?0 10 %v cc note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. symbol parameter commercial industrial military units min. max. min. max. min. max. v oh 1 (i oh = ? 10 ma) 2 2.4 v (i oh = ? 6 ma) 3.84 v (i oh = ? 4 ma) 3.7 3.7 v v ol 1 (i ol = 10 ma) 2 0.5 v (i ol = 6 ma) 0.33 0.40 0.40 v v il ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 v v ih 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v input transition time t r , t f 2 500 500 500 ns c io i/o capacitance 2, 3 10 10 10 pf standby current, i cc 4 (typical = 1 ma) 2 10 20 ma leakage current 5 ? 10 10 ? 10 10 ? 10 10 ? notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. includes worst-case 176 cpga package capacitance. v out = 0 v, f = 1 mhz. 4. all outputs unloaded. all inputs = v cc or gnd, typical i cc = 1 ma. i cc limit includes i pp and i sv during normal operation. 5. v out , v in = v cc or gnd. .com .com .com .com .com 4 .com u datasheet
v4.0 5 act ? 2 family fpgas package thermal characteristics the device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a pqfp 160-pin package at commercial temperature is as follows: power dissipation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc ? v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . an accurate determination of n and m is problematical because their values depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated below for commercial, worst case conditions. i cc v cc power 2 ma 5.25v 10.5 mw the static power dissipated by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33 v will generate 42 mw with all outputs driving low, and 140 mw with all outputs driving high. the actual dissipation will average somewhere between as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces package type pin count jc ja still air ja 300 ft/min units ceramic pin grid array 100 132 176 5 5 8 35 30 23 17 15 12 c/w c/w c/w ceramic quad flat pack 172 8 25 15 c/w plastic quad flat pack 1 100 144 160 13 15 15 48 40 38 40 32 30 c/w c/w c/w plastic leaded chip carrier 2 84 12 37 28 c/w very thin quad flat pack 3 100 12 43 35 c/w thin quad flat pack 4 176 15 32 25 c/w notes:(maximum power in still air) 1. maximum power dissipation for pqfp packages are 1.9 watts (100-pin), 2.3 watts (144-pin), and 2.4 watts (160-pin). 2. maximum power dissipation for plcc packages is 2.7 watts. 3. maximum power dissipation for vqfp packages is 2.3 watts. 4. maximum power dissipation for tqfp packages is 3.1 watts. max. junction temp. (c) ? max. commercial temp. ja (c/w) ---------------------------------------------------------------------------------------------------------------------------- - 150c ? 70c 33c/w --------------------------------- 2.4 w == .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 6v4.0 and load device inputs. an additional component of the active power dissipation is the totem-pole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by the equation 1. power ( w) = c eq * v cc 2 * f (1) where: c eq is the equivalent capacitance expressed in pf. v cc is the power supply in volts. f is the switching frequency in mhz. equivalent capacitance is calculated by measuring icc active at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of vcc. equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq values for actel fpgas modules (c eqm )5.8 input buffers (c eqi ) 12.9 output buffers (c eqo ) 23.8 routed array clock buffer loads (c eqcr )3.9 to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piece-wise linear summation over all components. power = v cc 2 * [(m * c eqm * f m ) modules +(n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 ](2) where: fixed capacitance values for actel fpgas (pf) r1 r2 device type routed_clk1 routed_clk2 a1225a 106 106.0 a1240a 134 134.2 a1280a 168 167.8 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. these guidelines are as follows: m = number of logic modules switching at fm n = number of input buffers switching at fn p = number of output buffers switching at fp q1 = number of clock loads on the first routed array clock q2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz logic modules (m) 80% of modules inputs switching (n) # inputs/4 outputs switching (p) # outputs/4 first routed array clock loads (q 1 ) 40%of sequential modules second routed array clock loads (q 2 ) 40%of sequential modules load capacitance (c l ) 35 pf average logic module switching rate (f m )f/10 average input switching rate (f n )f/5 average output switching rate (f p )f/10 average first routed array clock rate (f q1 )f average second routed array clock rate (f q2 ) f/2 .com .com .com .com .com 4 .com u datasheet
v4.0 7 act ? 2 family fpgas act 2 timing model* *values shown for a1240a-2 at worst-case commercial conditions. ? input module predicted routing delay output delays internal delays input delays t inh = 2.0 ns t insu = 4.0 ns i/o module d q t ingl = 4.7 ns t inyl = 2.6 ns t ird2 = 4.8 ns ? combinatorial logic module t pd = 3.8 ns sequential logic module i/o module t rd1 = 1.4 ns t dlh = 8.0 ns i/o module array clocks f max = 100 mhz combin- atorial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.4 ns t glh = 9.0 ns t dlh = 8.0 ns t enhz = 7.1 ns t rd1 = 1.4 ns t co = 3.8 ns t sud = 0.4 ns t hd = 0.0 ns t rd4 = 3.1 ns t rd8 = 4.7 ns predicted routing delays t ckh = 11.8 ns g g fo = 256 t rd2 = 1.7 ns .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 8v4.0 parameter measurement output buffer delays ac test loads input buffer delays module delays to ac test loads (shown below) d e tribuff in v cc gnd 50% pa d v ol v oh 1.5 v t dlh 50% 1.5 v t dhl e v cc gnd 50% pa d v ol 1.5 v t enzl 50% 10% t enlz e v cc gnd 50% pad gnd v oh 1.5 v t enzh 50% 90% t enhz v cc pad load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 50 pf to the output under test v cc gnd 50 pf to the output under test r to v cc for t plz /t pzl r to gnd for t phz /t pzh r = 1 k ? y inbuf pad 3 v 0 v 1.5 v y gnd v cc 50% t inyh 1.5 v 50% t inyl pa d s a b y s, a or b y gnd v cc 50% t plh y gnd gnd v cc 50% 50% 50% v cc 50% 50% t phl t phl t plh .com .com .com .com .com 4 .com u datasheet
v4.0 9 act ? 2 family fpgas sequential module timing characteristics flip-flops and latches note: d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge triggered) d e clk clr pre y d 1 g, clk e q pre, clr t wclka t wasyn t hd t suena t sud t rs t a t wclki t co t hena .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 10 v4.0 sequential timing characteristics (continued) input buffer latches output buffer latches g pad pad clk data g clk t inh clkbuf t insu t suext t hext ibdl data d g t outsu t outh pad obdlhs d g .com .com .com .com .com 4 .com u datasheet
v4.0 11 act ? 2 family fpgas timing derating factor (temperature and voltage) timing derating factor for designs at typical temperature (t j = 25 c) and voltage (5.0 v) temperature and voltage derating factors (normalized to worst-case commercial, t j = 4.75 v, 70 c) junction temperature and voltage derating curves (normalized to worst-case commercial, t j = 4.75v, 70 c) industrial military min. max. min. max. (commercial minimum/maximum specification) x 0.69 1.11 0.67 1.23 (commercial maximum specification) x 0.85 ? 55 ? 400 257085125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 note: this derating factor applies to all routing and propagation delays. 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 4.50 4.75 5.00 5.25 5.50 derating factor voltage (v) 125?c 85?c 70?c 25?c 0?c ?0?c ?5?c .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 12 v4.0 a1225a timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) logic module propagation delays 1 ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units t pd1 single module 3.8 4.3 5.0 ns t co sequential clk to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.1 1.2 1.4 ns t rd2 fo=2 routing delay 1.7 1.9 2.2 ns t rd3 fo=3 routing delay 2.3 2.6 3.0 ns t rd4 fo=4 routing delay 2.8 3.1 3.7 ns t rd8 fo=8 routing delay 4.4 4.9 5.8 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.5 5.0 6.0 ns t wasyn flip-flop (latch) asynchronous pulse width 4.5 5.0 6.0 ns t a flip-flop clock input period 9.4 11.0 13.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 105.0 90.0 75.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. .com .com .com .com .com 4 .com u datasheet
v4.0 13 act ? 2 family fpgas a1225a timing characteristics (continued) (worst-case commercial conditions) input module propagation delays ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. unit s t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.6 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.7 5.4 6.3 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 4.1 4.6 5.4 ns t ird2 fo=2 routing delay 4.6 5.2 6.1 ns t ird3 fo=3 routing delay 5.3 6.0 7.1 ns t ird4 fo=4 routing delay 5.7 6.4 7.6 ns t ird8 fo=8 routing delay 7.4 8.3 9.8 ns global clock network t ckh input low to high fo = 32 fo = 256 10.2 11.8 11.0 13.0 12.8 15.7 ns t ckl input high to low fo = 32 fo = 256 10.2 12.0 11.0 13.2 12.8 15.9 ns t pwh minimum pulse width high fo = 32 fo = 256 3.4 3.8 4.1 4.5 4.5 5.0 ns t pwl minimum pulse width low fo = 32 fo = 256 3.4 3.8 4.1 4.5 4.5 5.0 ns t cksw maximum skew fo = 32 fo = 256 0.7 3.5 0.7 3.5 0.7 3.5 ns t suext input latch external setup fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 256 7.0 11.2 7.0 11.2 7.0 11.2 ns t p minimum period fo = 32 fo = 256 7.7 8.1 8.3 8.8 9.1 10.0 ns f max maximum frequency fo = 32 fo = 256 130.0 125.0 120.0 115.0 110.0 100.0 mhz note: 1. these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typical designs across worst-case operating conditions. post-route timing analysis or simulation is requ ired to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the devic e prior to shipment. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 14 v4.0 a1225a timing characteristics (continued) (worst-case commercial conditions) output module timing ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units ttl output module timing 1 t dlh data to pad high 8.0 9.0 10.6 ns t dhl data to pad low 10.1 11.4 13.4 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.6 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.3 9.5 11.1 ns t glh g to pad high 8.9 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.1 11.5 13.5 ns t dhl data to pad low 8.4 9.6 11.2 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.6 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.3 9.5 11.1 ns t glh g to pad high 8.9 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf note: 1. delays based on 50 pf loading. 2. sso information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. .com .com .com .com .com 4 .com u datasheet
v4.0 15 act ? 2 family fpgas a1240a timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) logic module propagation delays 1 ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units t pd1 single module 3.8 4.3 5.0 ns t co sequential clk to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.4 1.5 1.8 ns t rd2 fo=2 routing delay 1.7 2.0 2.3 ns t rd3 fo=3 routing delay 2.3 2.6 3.0 ns t rd4 fo=4 routing delay 3.1 3.5 4.1 ns t rd8 fo=8 routing delay 4.7 5.4 6.3 ns sequential timing characteristics 3, 4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.5 6.0 6.5 ns t wasyn flip-flop (latch) asynchronous pulse width 4.5 6.0 6.5 ns t a flip-flop clock input period 9.8 12.0 15.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 100.0 80.0 66.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 16 v4.0 a1240a timing characteristics (continued) (worst-case commercial conditions) input module propagation delays ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.6 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.7 5.4 6.3 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 4.2 4.8 5.6 ns t ird2 fo=2 routing delay 4.8 5.4 6.4 ns t ird3 fo=3 routing delay 5.4 6.1 7.2 ns t ird4 fo=4 routing delay 5.9 6.7 7.9 ns t ird8 fo=8 routing delay 7.9 8.9 10.5 ns global clock network t ckh input low to high fo = 32 fo = 256 10.2 11.8 11.0 13.0 12.8 15.7 ns t ckl input high to low fo = 32 fo = 256 10.2 12.0 11.0 13.2 12.8 15.9 ns t pwh minimum pulse width high fo = 32 fo = 256 3.8 4.1 4.5 5.0 5.5 5.8 ns t pwl minimum pulse width low fo = 32 fo = 256 3.8 4.1 4.5 5.0 5.5 5.8 ns t cksw maximum skew fo = 32 fo = 256 0.5 2.5 0.5 2.5 0.5 2.5 ns t suext input latch external setup fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 256 7.0 11.2 7.0 11.2 7.0 11.2 ns t p minimum period fo = 32 fo = 256 8.1 8.8 9.1 10.0 11.1 11.7 ns f max maximum frequency fo = 32 fo = 256 125.0 115.0 110.0 100.0 90.0 85.0 mhz note: these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typical designs across worst-case operating conditions. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipme nt. .com .com .com .com .com 4 .com u datasheet
v4.0 17 act ? 2 family fpgas a1240a timing characteristics (continued) (worst-case commercial conditions) output module timing ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units ttl output module timing 1 t dlh data to pad high 8.0 9.0 10.6 ns t dhl data to pad low 10.1 11.4 13.4 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.7 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.2 11.5 13.5 ns t dhl data to pad low 8.4 9.6 11.2 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.7 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf note: 1. delays based on 50 pf loading. 2. sso information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 18 v4.0 a1280a timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) logic module propagation delays 1 ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units t pd1 single module 3.8 4.3 5.0 ns t co sequential clk to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.7 2.0 2.3 ns t rd2 fo=2 routing delay 2.5 2.8 3.3 ns t rd3 fo=3 routing delay 3.0 3.4 4.0 ns t rd4 fo=4 routing delay 3.7 4.2 4.9 ns t rd8 fo=8 routing delay 6.7 7.5 8.8 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.5 6.0 7.0 ns t wasyn flip-flop (latch) asynchronous pulse width 5.5 6.0 7.0 ns t a flip-flop clock input period 11.7 13.3 18.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 85.0 75.0 50.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. .com .com .com .com .com 4 .com u datasheet
v4.0 19 act ? 2 family fpgas a1280a timing characteristics (continued) (worst-case commercial conditions) input module propagation delays ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.7 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.8 5.4 6.3 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 4.6 5.1 6.0 ns t ird2 fo=2 routing delay 5.2 5.9 6.9 ns t ird3 fo=3 routing delay 5.6 6.3 7.4 ns t ird4 fo=4 routing delay 6.5 7.3 8.6 ns t ird8 fo=8 routing delay 9.4 10.5 12.4 ns global clock network t ckh input low to high fo = 32 fo = 384 10.2 13.1 11.0 14.6 12.8 17.2 ns t ckl input high to low fo = 32 fo = 384 10.2 13.3 11.0 14.9 12.8 17.5 ns t pwh minimum pulse width high fo = 32 fo = 384 5.0 5.8 5.5 6.4 6.6 7.6 ns t pwl minimum pulse width low fo = 32 fo = 384 5.0 5.8 5.5 6.4 6.6 7.6 ns t cksw maximum skew fo = 32 fo = 384 0.5 2.5 0.5 2.5 0.5 2.5 ns t suext input latch external setup fo = 32 fo = 384 0.0 0.0 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 7.0 11.2 7.0 11.2 7.0 11.2 ns t p minimum period fo = 32 fo = 384 9.6 10.6 11.2 12.6 13.3 15.3 ns f max maximum frequency fo = 32 fo = 384 105.0 95.0 90.0 80.0 75.0 65.0 mhz note: these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typical designs across worst-case operating conditions. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipme nt. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 20 v4.0 a1280a timing characteristics (continued) (worst-case commercial conditions) output module timing ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. units ttl output module timing 1 t dlh data to pad high 8.1 9.0 10.6 ns t dhl data to pad low 10.2 11.4 13.4 ns t enzh enable pad z to high 9.0 10.0 11.8 ns t enzl enable pad z to low 11.8 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.3 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.3 11.5 13.5 ns t dhl data to pad low 8.5 9.6 11.2 ns t enzh enable pad z to high 9.0 10.0 11.8 ns t enzl enable pad z to low 11.8 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.3 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf note: 1. delays based on 50 pf loading. 2. sso information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. .com .com .com .com .com 4 .com u datasheet
v4.0 21 act ? 2 family fpgas pin description clka clock a (input) ttl clock input for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) ttl clock input for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground low supply voltage. i/o input/output (input, output) the i/o pin functions as an input, output, three-state, or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the als software. mode mode (input) the mode pin controls the use of multifunction pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide actionprobe capability, the mode pin should be terminated to gnd through a 10k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra probe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb probe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. v cc 5.0v supply voltage high supply voltage. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 22 v4.0 package pin assignments 84-pin plcc signal a1225a function a1240a function a1280a function 2 clkb, i/o clkb, i/o clkb, i/o 4 prb, i/o prb, i/o prb, i/o 6 gnd gnd gnd 10 dclk, i/o dclk, i/o dclk, i/o 12 mode mode mode 22 vcc vcc vcc 23 vcc vcc vcc 28 gnd gnd gnd notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 184 84-pin plcc .com .com .com .com .com 4 .com u datasheet
v4.0 23 act ? 2 family fpgas 43 vcc vcc vcc 49 gnd gnd gnd 63 gnd gnd gnd 64 vcc vcc vcc 65 vcc vcc vcc 70 gnd gnd gnd 76 sdi, i/o sdi, i/o sdi, i/o 81 pra, i/o pra, i/o pra, i/o 83 clka, i/o clka, i/o clka, i/o 84 vcc vcc vcc package pin assignments 84-pin plcc signal a1225a function a1240a function a1280a function notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 184 84-pin plcc .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 24 v4.0 package pin assignments (continued) 100-pin pqfp pin number a1225a function pin number a1225a function 2 dclk, i/o 66 vcc 4mode 67vcc 9gnd 72gnd 16 vcc 79 sdi, i/o 17 vcc 84 gnd 22 gnd 87 pra, i/o 34 gnd 89 clka, i/o 40 vcc 90 vcc 46 gnd 92 clkb, i/o 57 gnd 94 prb, i/o 64 gnd 96 gnd 65 vcc notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 100-pin pqfp 1 100 .com .com .com .com .com 4 .com u datasheet
v4.0 25 act ? 2 family fpgas package pin assignments (continued) 144-pin pqfp 144 1 144-pin pqfp .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 26 v4.0 144-pin pqfp pin number a1240a function pin number a1240a function 2mode 89vcc 9gnd 90vcc 10 gnd 91 vcc 11 gnd 92 vcc 18 vcc 93 vcc 19 vcc 100 gnd 20 vcc 101 gnd 21 vcc 102 gnd 28 gnd 110 sdi, i/o 29 gnd 116 gnd 30 gnd 117 gnd 44 gnd 118 gnd 45 gnd 123 pra, i/o 46 gnd 125 clka, i/o 54 vcc 126 vcc 55 vcc 127 vcc 56 vcc 128 vcc 64 gnd 130 clkb, i/o 65 gnd 132 prb, i/o 79 gnd 136 gnd 80 gnd 137 gnd 81 gnd 138 gnd 88 gnd 144 dclk, i/o notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. .com .com .com .com .com 4 .com u datasheet
v4.0 27 act ? 2 family fpgas package pin assignments (continued) 160-pin pqfp 160 1 160-pin pqfp .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 28 v4.0 160-pin pqfp pin number a1280a function pin number a1280a function 2 dclk, i/o 69 gnd 6vcc 80gnd 11 gnd 86 vcc 16 prb, i/o 89 gnd 18 clkb, i/o 98 vcc 20 vcc 99 gnd 21 clka, i/o 109 gnd 23 pra, i/o 114 vcc 30 gnd 120 gnd 35 vcc 125 gnd 38 sdi, i/o 130 gnd 40 gnd 135 vcc 44 gnd 138 vcc 49 gnd 139 vcc 54 vcc 140 gnd 57 vcc 145 gnd 58 vcc 150 vcc 59 gnd 155 gnd 60 vcc 159 mode 61 gnd 160 gnd 64 gnd notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. .com .com .com .com .com 4 .com u datasheet
v4.0 29 act ? 2 family fpgas package pin assignments (continued) 100-pin vqfp 100-pin vqfp pin number a1225a function pin number a1225a function 2mode 65vcc 7gnd 70gnd 14 vcc 77 sdi, i/o 15 vcc 82 gnd 20 gnd 85 pra, i/o 32 gnd 87 clka, i/o 38 vcc 88 vcc 44 gnd 90 clkb, i/o 55 gnd 92 prb, i/o 62 gnd 94 gnd 63 vcc 100 dclk, i/o 64 vcc notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 1 100-pin vqfp 100 .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 30 v4.0 package pin assignments (continued) 176-pin tqfp 1 176-pin tqfp 176 .com .com .com .com .com 4 .com u datasheet
v4.0 31 act ? 2 family fpgas 176-pin tqfp pin number a1240a function a1280a function pin number a1240a function a1280a function 1 gnd gnd 101 nc nc 2 mode mode 103 nc i/o 8nc nc 106gnd gnd 10 nc i/o 107 nc i/o 11 nc i/o 108 nc i/o 13 nc vcc 109 gnd gnd 18 gnd gnd 110 vcc vcc 19 nc i/o 111 gnd gnd 20 nc i/o 112 vcc vcc 22 nc i/o 113 vcc vcc 23 gnd gnd 114 nc i/o 24 nc vcc 115 nc i/o 25 vcc vcc 116 nc vcc 26 nc i/o 121 nc nc 27 nc i/o 124 nc i/o 28 vcc vcc 125 nc i/o 29 nc i/o 126 nc nc 33 nc nc 133 gnd gnd 37 nc i/o 135 sdi, i/o sdi, i/o 38 nc nc 136 nc i/o 45 gnd gnd 140 nc vcc 52 nc vcc 143 nc i/o 54 nc i/o 144 nc i/o 55 nc i/o 145 nc nc 57 nc nc 147 nc i/o 61 nc i/o 151 nc i/o 64 nc i/o 152 pra, i/o pra, i/o 66 nc i/o 154 clka, i/o clka, i/o 67 gnd gnd 155 vcc vcc 68 vcc vcc 156 gnd gnd 74 nc i/o 158 clkb, i/o clkb, i/o 77 nc nc 160 prb, i/o prb, i/o 78 nc i/o 161 nc i/o 80 nc i/o 165 nc nc 82 nc vcc 166 nc i/o 86 nc i/o 168 nc i/o 89 gnd gnd 170 nc vcc 96 nc i/o 173 nc i/o 97 nc i/o 175 dclk, i/o dclk, i/o notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 32 v4.0 package pin assignments (continued) 172-pin cqfp 172-pin cqfp pin number a1280a function pin number a1280a function 1 mode 107 vcc 7 gnd 108 gnd 12 vcc 109 vcc 17 gnd 110 vcc 22 gnd 113 vcc 23 vcc 118 gnd 24 vcc 123 gnd 27 vcc 131 sdi, i/o 32 gnd 136 vcc 37 gnd 141 gnd 50 vcc 148 pra, i/o 55 gnd 150 clka, i/o 65 gnd 151 vcc 66 vcc 152 gnd 75 gnd 154 clkb, i/o 80 vcc 156 prb, i/o 98 gnd 161 gnd 103 gnd 166 vcc 106 gnd 171 dclk, i/o notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 172-pin cqfp pin #1 index 172 1 .com .com .com .com .com 4 .com u datasheet
v4.0 33 act ? 2 family fpgas package pin assignments (continued) 100-pin cpga pin number a1225a function pin number a1225a function a4 prb, i/o e11 vcc a7 pra, i/o f3 vcc b6 vcc f9 vcc c2 mode f10 vcc c3 dclk, i/o f11 gnd c5 gnd g1 vcc c6 clka, i/o g3 gnd c7 gnd g9 gnd c8 sdi, i/o j5 gnd d6 clkb, i/o j7 gnd d10 gnd k6 vcc e3 gnd note: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 1 a 234567891011 b c d e f g h j k l a b c d e f g h j k l 100-pin cpga 1234567891011 orientation pin .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 34 v4.0 package pin assignments (continued) 132-pin cpga pin number a1240a function pin number a1240a function a1 mode g2 vcc b5 gnd g3 vcc b6 clkb, i/o g4 vcc b7 clka, i/o g10 vcc b8 pra, i/o g11 vcc b9 gnd g12 vcc b12 sdi, i/o g13 vcc c3 dclk, i/o h13 gnd c5 gnd j2 gnd c6 prb, i/o j3 gnd c7 vcc j11 gnd c9 gnd k7 vcc d7 vcc k12 gnd e3 gnd l5 gnd e11 gnd l7 vcc e12 gnd l9 gnd f4 gnd m9 gnd notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 132-pin cpga a b c d e f g h j k l m n a b c d e f g h j k l m n orientation pin 1 2345678910111213 1 2345678910111213 .com .com .com .com .com 4 .com u datasheet
v4.0 35 act ? 2 family fpgas package pin assignments (continued) 176-pin cpga pin number a1280a function pin number a1280a function a9 clka, i/o h2 vcc b3 dclk, i/o h3 vcc b8 clkb, i/o h4 gnd b14 sdi, i/o h12 gnd c3 mode h13 vcc c8 gnd h14 vcc c9 pra, i/o j4 vcc d4 gnd j12 gnd d5 vcc j13 gnd d6 gnd j14 vcc d7 prb, i/o k4 gnd d8 vcc k12 gnd d10 gnd l4 gnd d11 vcc m4 gnd d12 gnd m5 vcc e4 gnd m6 gnd e12 gnd m8 gnd f4 vcc m10 gnd f12 gnd m11 vcc g4 gnd m12 gnd g12 vcc n8 vcc notes: 1. all unlisted pin numbers are user i/os. 2. mode pin should be terminated to gnd through a 10k resistor to enable actionprobe usage, otherwise it can be terminated direc tly to gnd. 1 a 234567891011 b c d e f g h j k l 176-pin cpga 1234567891011 12 12 13 13 14 14 15 15 m n p r a b c d e f g h j k l m n p r .com .com .com .com .com 4 .com u datasheet
act ? 2 family fpgas 36 v4.0 list of changes the following table lists critical changes that were made in the current version of the document. data sheet categories in order to provide the latest information to designers, some data sheets are published before data has been fully characterized. these data sheets are marked as ? advanced ? or preliminary ? data sheets. the definition of these categories are as follows: advanced the data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. preliminary the data sheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) the data sheet contains information that is considered to be final. previous version changes in current version (production (unmarked) v4.0.1 ? web-only) page unspecified in the 176-pin cpga package, pin a3 was incorrectly assigned as clka, i/o. a3 is a user i/o. pin a9 is clka, i/o 35 .com .com .com .com .com 4 .com u datasheet
v4.0 37 act ? 2 family fpgas .com .com .com .com .com 4 .com u datasheet
actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel europe ltd. daneshill house, lutyens close basingstoke, hampshire rg24 8ag united kingdom tel: +44 (0)1256 305600 fax: +44 (0)1256 355420 actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel asia-pacific exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81 03-3445-7671 fax: +81 03-3445-7668 5172104-6/12.00 .com .com .com .com 4 .com u datasheet

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